Integrated circuit memory devices are widely used for consumer, commercial and many other applications. Integrated circuit memory devices store data able to be retrieved therefrom, which are roughly classified into random-access memories (RAMs) and read-only memories (ROMs). The RoAMs are volatile memory devices that do not retain data when power is suspended or interrupted, including dynamic RAMs, and static RAMs. The ROMs have nonvolatile properties keeping data even without power being supplied, including programmable ROMs, erasable and programmable ROMs, electrically erasable and programmable ROMs, and flash memories. The flash memory devices may be classified into NAND and NOR types.
FIG. 1 is a block diagram showing a general configuration of a NAND flash memory device. As shown in FIG. 1, the flash memory device 10 is includes a memory cell array 12, a row decoder 14, and a page buffer 16. The memory cell array 12 is composed of a plurality of memory cells connected with wordlines WL0˜WLn-1 and bitlines BL0˜BLn-1. The wordlines WL0˜WLn-1 are driven by a row decoder 14 and the bitlines BL0˜BLn-1 are driven by the page buffer 16.
Technologies have recently been developed that are capable of selectively storing multi-bit data in a single memory cell of the NAND flash memory device. The memory cell is set in one of multiple states in accordance with a predetermined data condition, which is called multi-level cell (MLC). For example, a memory cell storing 2-bit data is conditioned in one of four states, ‘11’, ‘10’, ‘00’, or ‘01’.
As the memory cell of the NAND flash memory device is able to store 1-bit data (i.e., a single bit) or multi-bit data, the page buffer 16 may be designed with different patterns in accordance with the bit pattern, i.e., 1-bit or multi-bit, of the NAND flash memory device. For instance, a page buffer for processing 1-bit data may include a single latch, while a page buffer for processing 2-bit data may include two latches.